1. Field of the Invention
The present invention generally relates to a semiconductor device and more particularly to a semiconductor LSI device which can be easily tested when it is mounted on a circuit board.
2. Description of the Related Art
In general, semiconductor integrated circuit (IC) devices have to be tested after fabrication thereof for the purpose of checking whether the devices can operate in the manner for which they were designed. As the circuit configuration of the semiconductor IC device becomes more complicated with the integration density being increased, testing of the circuit operation of the device becomes more difficult. Consequently, preparation of test patterns for testing all the circuit functions requires very laborious and time consuming procedures. Under the circumstances, attempts have been made to realize IC circuit structures which can facilitate testing. By way of example, functional means are additionally incorporated which allow memory or storage elements included in a logic circuit to be set in desired states arbitrarily in response to signals applied externally or allow the states of the storage elements to be directly read out. A complicated logic circuit is separated into a group of storage elements and combinational logic circuits.
With a view to facilitating the testing of the combinational logic circuits, there has been proposed a so-called scan-path type circuit structure in which all flip-flops (latches) incorporated in a large scale IC or LSI are adapted to operate as shift registers upon testing of the LSI. Reference may be made to, for example, Japanese Patent Application Laid-Open No. 90270/1981 (JP-A-56-90270). In the case of this known circuit structure, such switching control means is provided which allows scan-in data applied to a plurality of signal terminals destined usually for data input/output to be directly set in a plurality of flip-flops while allowing the contents of the flip-flops to be directly transferred to the signal terminals to thereby realize a scan-out operation at a high speed.
It is however noted that no consideration has heretofore been paid to the testing or diagnosing a plurality of semiconductor LSI devices which are mounted or packed on a printed circuit board. This is because the logic scale of the circuit including a number of the semiconductor LSI devices mounted on the printed circuit board becomes very large, making it extremely difficult to prepare diagnosis patterns for testing the circuit, which requires an enormous amount of pattern data, giving rise to a problem.
For the reason mentioned above, a method has been extensively adopted according to which individual LSIs mounted on the printed circuit board are diagnosed with the aid of a so-called in-circuit tester. However, the test by using the in-circuit tester must be performed for each of LSIs individually and separately, involving time consuming labor. Besides, even when a defect in contact is present between a pin of an LSI and a wiring conductor on a printed circuit board, there is a possibility that such defect might not be detected because the pin might be pressed against the solder island on the printed circuit upon testing, whereby good contact is temporarily established. In that case, no contact failure is indicated, which is, of course another disadvantage.
In other words, although the printed circuit board having a plurality of LSIs mounted thereon should desirably be tested in the state as it is, there has been available no convenient method or means capable of conducting such test or diagnosis.